1. Field of Invention
The present invention relates to a method of fabricating read-only-memory (ROM). More particularly, the present invention relates to a method of fabricating a mask read-only-memory (ROM).
2. Description of Related Art
Read-only-memory (ROM) is a type of non-volatile memory whose data is retained even when power is turned off. Due to such versatility, ROM is an indispensable device for booting up many electronic products before conducting any normal operations. One of the most common types of ROM is the mask ROM. Typically, a mask ROM uses a conductive transistor to serve as a memory cell. To program the mask ROM, ions are selectively implanted into specified channel regions so that the threshold voltages of these transistors are adjusted. Memory data is stored inside these memory cells according to whether the respective channel regions of these cells are on or off.
In general, the memory cell array of a mask ROM is fabricated with a particular transistor configuration. The mask ROM constructed from an array of transistors can have the following problems.
Due to the demand for a high-quality silicon substrate and gate oxide layer underneath the transistors, conditions for fabricating the transistor array must be strictly adhered to. Stacking an additional layer over such an array of transistor is difficult.
Furthermore, in the presence of leakage current, a memory cell array fabricated from transistors, the window for decoding a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d data is not very clear. In other words, decoding errors may occur.
In addition, the bit lines of a transistor memory cell array are fabricated by implanting dopants into the substrate. However, as devices continue to be miniaturized, junction depth will be shallower leading to rise in bit line resistance. Ultimately, operating efficiency of the device may be affected.
Accordingly, one object of the present invention is to provide a mask read-only-memory (mask ROM) structure and method of fabricating the same that reduces device dimension and increases device integration.
A second object of this invention is to provide a mask ROM structure and method of fabricating the same that provides a clearer decoding capacity and hence increases the decoding window.
A third object of this invention is to provide a mask ROM structure and method of fabricating the same that increases the operating speed of the device.
A fourth object of this invention is to provide a mask ROM structure and method of fabricating the same that simplifies the mask ROM fabrication process.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of fabricating a mask ROM. First, a substrate is provided. Thereafter, gate dielectric and a plurality of first conductive strips are sequentially formed over the substrate. A first dielectric layer is formed over the substrate and the first conductive strips. The first dielectric layer is patterned to form a plurality of first coding openings. Each first coding opening exposes the first conductive layer. A plurality of first wells is formed in the first conductive layer at the bottom of the first coding openings. A plurality of second conductive strips is formed over the first dielectric layer and inside the first coding openings to connect electrically with the first wells and form a first memory cell array.
In the aforementioned method, a second dielectric layer may form over the first dielectric layer and the second conductive strips after forming the first memory cell array. Thereafter, a plurality of third conductive strips is formed over the second dielectric layer. A third dielectric layer is formed over the second dielectric layer and the third conductive strips. The third dielectric layer is patterned to form a plurality of second coding openings. Each second coding opening exposes the third conductive layer. A plurality of second wells is formed in the third conductive strip at the bottom of the second coding openings. A plurality of fourth conductive strips is formed over the third dielectric layer and inside the second coding openings to connect electrically with the second wells and form a second memory cell array.
This invention also provides a mask read-only-memory (mask ROM) structure. The mask ROM has at least a substrate, a plurality of gate dielectric strips, a plurality of first conductive strips, a first dielectric layer, a plurality of first wells and a plurality of second conductive strips. The gate dielectric layers are positioned over the substrate. The first conductive strips are positioned over the gate dielectric layers. The first dielectric layer is positioned over the substrate and the first conductive strips. The first dielectric layer has a plurality of first coding openings that exposes the first conductive strips. The first wells are located in the first conductive strips at the bottom of first code openings. The second conductive strips are positioned over the first dielectric layer and inside the first coding openings. The second conductive strips electrically connect with the respective first wells. The gate dielectric layers, the first conductive strips, the first dielectric layer, the first wells and the second conductive strips together form a first memory cell array.
The aforementioned mask ROM structure may further include a second dielectric layer, a plurality of third conductive strips, a third dielectric layer, a plurality of second wells, a plurality of fourth conductive strips. The second dielectric layer is positioned over the first dielectric layer and the second conductive strips. The third conductive strips are positioned over the second dielectric layer. The third dielectric layer is positioned over the second dielectric layer and the third conductive strips. The third dielectric layer has a plurality of second coding openings that exposes the third conductive strips. The second wells are located in the third conductive strips at the bottom of the second coding openings. The fourth conductive strips are positioned over the third dielectric layer and inside the second coding openings. The fourth conductive strips connect electrically with the respective second wells. The second dielectric layer, the third conductive strips, the third dielectric layer, the second wells and the fourth conductive strips together form a second memory cell array.
In addition, in the aforementioned mask ROM structure and method of fabricating the same, a plurality of memory cell arrays may stack on top of the second memory cell array. Furthermore, the second conductive layers and the fourth conductive layers may be fabricated using a metallic material such as aluminum, tungsten or copper with a non-metallic material such as N+ doped polysilicon.
This invention also provides a method of decoding mask read-only-memory (mask ROM). The mask ROM has at least a plurality of word lines, a plurality of wells over the word lines and a plurality of bit lines. The word lines are doped differently from the wells (P+ type). The bit lines are perpendicular to the word lines at a different height level. A portion of the junctions between the bit lines and the word lines is electrically connected to the well. The decoding method includes applying a first voltage to the bit line corresponding to a decoding location and applying a second voltage to the bit lines outside the decoding location such that the first voltage is greater than the second voltage. At the same time, a third voltage is applied to the word line corresponding to the decoding location and a fourth voltage is applied to the word lines outside the decoding location such that the fourth voltage is greater than the third voltage.
In this invention, the cells in the memory cell array of the mask ROM are diodes. Hence, the memory cell array may stack on top of each other to form a three-dimensional structure. Consequently, size of each memory cell can be reduced and the level of integration of the memory device can be increased.
Furthermore, the decoding regions (the diodes) with implant ions are regarded as a logic state xe2x80x9c1xe2x80x9d and those decoding regions without implanted ions are regarded as a logic state xe2x80x9c0xe2x80x9d. Thus, determining the logic value (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) in the memory cell is much easier compared with a conventional transistor memory cell array. In other words, the decoding window is larger.
In addition, the bit lines may be fabricated using a metallic material. Hence, compared with a bit line formed by substrate doping, the bit lines have a lower resistance and a higher operating speed.
Since there is no need to fabricate transistors, processing demands are simpler and less stringent. Ultimately, the fabrication of the mask ROM in this invention is very much simplified.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.